1. Field of the Invention
The present invention relates to a delay adjustment circuit having an adjustable waveform that is used to generate a clock signal employed during digital processing and a clock generating circuit that generates a clock having a pre-determined frequency using this delay adjustment circuit.
2. Description of the Related Art
In a conventional clock generating circuit, in order to generate a clock that is 0.5×N (N=3, 4, 5, . . . ) times the operating frequency of a reference clock, a PLL circuit is frequently used. As shown in FIG. 14, a generally used PLL circuit 800 is formed by a phase comparing circuit 802, a low pass filter (LPF) 804, a voltage control oscillator (VCO) 806, and a 1/N divider 808. Reference numeral 810 is a clock distributing circuit that supplies to each part the clock generated by the PPL circuit 800.
This PLL 800 generates a clock 807 having an operating frequency that is N-times the reference clock that is input into the PLL circuit 800. From the clock 807 generated by the PPL circuit 800, the output clock 809 is supplied to each block within the semiconductor integrated circuit device (LSI) via the clock distributing circuit 810. The comparison signal 810, which is the output clock 809 divided by 1/N by the 1/N divider 808, is fed back, and the phase difference between it and the reference clock 801 is detected by the phase comparing circuit 802.
The phase difference detection pulse 803, which is the output of the phase comparing circuit 802, has a pulse width that depends on the phase difference, and is integrated by the low pass filter 804, and the control voltage 805 of the VCO having a value that depends on this pulse width is input into the voltage control oscillator (VCO) 806. In addition, depending on the phase difference between the reference clock 801 and the comparison signal 810, the oscillating frequency of the voltage control oscillator circuit 806 changes, and finally, the output 809 of the clock distributing circuit 810 is controlled so as to be in synchronism with the reference clock 801.
In this manner, the PPL circuit can be used to compensate the variation in the semiconductor integrated circuit in the capacity, wiring thickness, wiring width, etc., of the transistors that are produced during manufacture of the semiconductor integrated circuit. However, the PPL circuit exhibits the phenomenon that the width of the output waveform increases and decreases through time when the power source voltage increases and decreases accompanying the fluctuation in the operation rate of the adjacent circuits. This is called jitter. Even while the PPL circuit is operating in synchronism with the reference clock 801, the jitter does not necessarily disappear after using the PLL circuit.
In addition, in the case that the waveform of the reference clock 801 differs from the expected waveform due to fluctuation in the duty ratio, there are cases when the phase comparing circuit does not function as expected.
There is the problem that if the jitter is large and the duty function differs from estimates assumed during the design, the manufactured LSI may not operate, and then must be remanufactured or redesigned.